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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 141
PIC16F946
FIGURE 11-4:
USART RECEIVE BLOCK DIAGRAM
FIGURE 11-5:
ASYNCHRONOUS RECEPTION
TABLE 11-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0Ch
PIR1
EEIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
1Ah
RCREG USART Receive Data Register
0000 0000
8Ch
PIE1
EEIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
Legend:
x
= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT/
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷64
÷16
or
Stop
Start
(8)
7
1
0
RX9
FOSC
SDI/SDA/SEG8
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
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